In certain applications it is beneficial to run some parts of an integrated circuit (IC) at a higher clock frequency than the majority of the chip. FIG. 1 illustrates an example of clock signals, clk1x 110 and clk2x 120, where clock signal clk2x 120 is twice the frequency of clock signal clk1x 110. Examples of integrated circuits in which portions of the device may operate at a higher frequency include, for example, high performance microprocessors, digital signal processors (DSP), and IC's used for high speed data communications. To generate the higher clock frequencies used in such applications, phase locked loops (PLLs) or delay locked loops (DLLs) may be used. The jitter performance of these PLLs and DLLs is usually one of the key design parameters, and customarily the jitter is minimized to provide equal cycle times, independent of power supply noise. This is typically achieved by using a separate power supply for the higher frequency clock circuitry, or by using circuits having a propagation delay independent of the power supply level.
In many IC devices, the on-chip power supply voltage has a pronounced ripple at the clock frequency of that portion of the device that dominates the power dissipation. This ripple is caused by the clock controlled periodic supply current, which passes through on-chip resistive supply networks, and through the package inductances. The ripple results in a lower than average power supply voltage (i.e., a droop region), during the times when the logic consumes its peak current. The IC circuitry may then experience some inductive overshoot (i.e., an overshoot region) above the average power supply voltage, when the instantaneous current consumed by the logic tapers off. In an edge triggered design, the droop region usually appears close to the rising clock edge, when the majority of the device logic comprises rising-edge-triggered flip-flops.
The propagation delay of logic gates in an IC is a function of the power supply voltage at the time when the circuit evaluates. Higher power supply voltages reduce propagation delay, lower supply voltages result in increased propagation delay.
When one portion of an integrated circuit operates at a higher frequency (e.g. twice the frequency) than another portion that consumes the majority of the power, the higher frequency block is forced to operate in the droop region of the power supply ripple caused by the portion of the circuit that consumes the largest amount of power. FIG. 2 illustrates the outline of an IC 210 comprising a smaller portion 230 that may operate using a higher speed clock than the portion 220 of the IC 210 that consumes the majority of the power. Such a situation typically forces an IC designer to limit the operating speed of higher speed portion 230 of the IC 210 based upon logic propagation delays available at the lower, droop region power supply voltages caused by the large power consuming portion 220, or to incorporate separate sources of power or additional noise reduction circuitry to minimize power supply noise. The minimum power supply voltage in the droop region may be substantially lower than the average supply level, impacting overall device performance, or the additional noise reduction measures may add cost to the device. This design problem can be expected to become more and more pronounced as the device density of ICs increases, the power supply voltages are scaled down, and power supply currents grow.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.